In general, the calculation or computing, such as, division is carried out in a repetitive type; in the similar manner to that with using figures written down on paper on a desk. The division of such the repetitive type of calculation can be divided in the types thereof, roughly into three (3); such as, a pull-back method, a pull-away method, and a SRT method, for example. Though being common with upon the principle of calculations, however those methods are fit to the high-speed calculation, in such the order as was mentioned above, due to use of redundancy of the quotient digit. Further, there is a convergence method other than those, however explanation will be omitted herein.
First, explanation will be given in the pull-back method. Assuming a dividend to be a partial remainder, a divisor is subtracted from the partial remainder, and if the result is a positive or zero (0), the quotient digit is made to be “1”. And, if being negative, the quotient digit is made to “0”, thereby turning back to an original value by adding the divisor subtracted again (this is so-called the “pull-back”). A left-hand side shifting is made to double the partial remainder (i.e., two (2) times), and then the next quotient digit is obtained, and this is repeated thereafter. Ten (10) times on the calculation with figure on paper corresponds to two (2) times of the 1 bit left-hand side shifting. In this pull-back method, since it is always necessary to add the divisor, so as to pull back, therefore if the partial remainder is negative, there is a limit on the high-speed division calculation.
On the contrary to this, it is the pull-away method, in which a negative value is provided for the quotient digit, such as, “−1” or “1”, for example, thereby eliminating the correction by the pull-back of the partial remainder. Since the quotient digit includes “−1”, there is a necessity of providing a quotient producing circuit for producing the quotient of only “0” or “1”. With this pull-away method, the quotient digit must be determined upon a result of subtraction of the partial remainder and the divisor, similar to the pull-back method mentioned above, therefore the high-speed processing is also difficult when the partial remainder and the divisor are large in the bit widths thereof. This pull-away method is described, for example, in Japanese Patent Laying-Open No. Hei 4-172526 (1992) “FLOATING POINT DIVIDER”, which will be mentioned later.
While, the SRT method is one, in which “−1”, “0” or “−1” is taken to be the quotient digit, so as to normalize the divisor and the dividend, thereby enabling the determination of the quotient digit at high-speed with using a several upper bits of the partial remainder. The calculation method by using this SRT method is described, for example, in Japanese Patent Laying-Open No. Hei 6-290030 (1994) “DIVIDER APPARATUS”, Japanese Patent Laying-Open No. Hei 9-69040 (1997) “CIRCUIT FOR CONDUCTING SQUARE ROOT CALCULATION/DIVISION OF RADIX 2 BY 3 STAGE OVERLAPPING WITH, EACH HAVING INTERFERENTIAL CALCULATION”, Japanese Patent Laying-Open No. Hei 9-91270 (1997) “COMPUTING UNIT”, and Japanese Patent Laying-Open No. Hei 10-187420 (1998) “DIVISION/SQUARE ROOT EXTRACTION COMPUTING UNIT” by the present inventors, etc.
On the other hand, as a method for duplicating the performance of a single precision calculation, by enabling the single precision calculation in the lower bits of the computing or calculating unit having double precision bit width, which is not used, there is also disclosed a computing unit, in which a small-scaled circuit is added to the floating point divider of the double precision, as shown in the Japanese Patent Laying-Open No. Hei 4-172526 (1992) relating to the pull-back method mentioned above, thereby processing two (2) floating point divisions of the single precision, in parallel. The adding/subtracting computing unit is divided into an upper one and a lower one, for conducting the respective single precision calculation therewith. Also, with the partial remainder, selection is made on whether to be added or subtracted with respect to the divisor, depending on the respective signs at the upper and the lower thereof. When being under the double precision, it is so constructed that a result can be obtained, which is same to that obtained by means of the computing unit of the double precision width, by selecting the sign at the upper side and also at the lower side, and transferring carrier from the lower side to the upper side.
Though this Japanese Patent Laying-Open No. Hei 4-172526 (1992) discloses therein the floating point dividing apparatus, being very effective for conducting the single precision calculations in parallel, but there is still an aspect in the calculating method, to be further improved with.
Namely, the pull-away method is applied into the calculation of the partial remainder from a viewpoint of the circuit structure, and the positive or negative of the partial remainder is determined upon the sign of the partial remainder, thereby determining on whether addition or subtraction is made with the divisor. However, upon determining on the positive/negative of the partial remainder by means of the sign of the partial remainder, it is necessary to propagate the partial remainder, with carrying up all the bits thereof, and then it takes much time for processing, therefore it has a drawback that it is difficult to process it at high-speed. Further, in this Japanese Patent Laying-Open No. Hei 4-172526 (1992), no disclosure is made on a manner or method for executing the calculation for extracting the square root at the high-speed.
An object, according to the present invention, is to provide a high-speed computing unit, such as, a divider, a square root unit, and also to provide an electronic circuit device using thereof.
The object in more details thereof, according to the present invention, is to provide a high-speed computing unit, enabling single-precision one (1) calculation, single precision two (2) calculations, and double precis ion calculation therewith, and also to provide an electronic circuit device using thereof.
Further the object, in more details thereof, according to the present invention, is to provide a computing unit, such as, a SRT computing unit of high-precision and high-speed, in particular, a floating point divider and a square root computing unit, etc., with using the SRT method having the double precision bit width, and also to provide an electronic circuit device using thereof.